Introduction
Via-in-pad is a PCB design technique that places a via directly within a surface mount pad. This allows routing between layers without requiring space adjacent to the pad for a separate via. Via-in-pad can help reduce routing congestion and optimize board space utilization, making it an important technique for high density PCBs. Properly implementing via-in-pad requires consideration of electrical, thermal, and manufacturing factors.
Benefits of Via-in-Pad
Using via-in-pad offers several advantages:
Space Savings
By placing vias within pads, no additional space is required for drilling and plating separate via holes. This allows higher component density and utilization of the entire board area for routing. Via-in-pad is especially beneficial when routing high pin count components like BGAs.
Routing Simplification
With via-in-pad, traces can transition between layers directly below components. This avoids the need to route around pads just to access a via. The result is shorter, simpler routing paths.
Reduced Layer Count
By enabling easier routing access between layers, via-in-pad can reduce the number of layers required for complex designs. Fewer layers lowers costs.
Improved Signal Integrity
By eliminating the stub created by a discrete via, via-in-pad allows smoother impedance transitions between layers. This enhances signal quality in high-speed designs.
Better Thermal Performance
A thermal path is created from the pad through all layers the via passes through. This facilitates heat dissipation, improving the thermal characteristics of packages like QFNs and LGAs.
Smaller Overall Board Size
The space savings and routing benefits provided by via-in-pad allow reducing the x-y board dimensions required for complex routing.
Manufacturability
Modern manufacturing processes are optimized for via-in-pad. This includes factors like layer-to-layer alignment and plating reliability.
Design Considerations
While via-in-pad provides many benefits, the technique also introduces constraints that impact the PCB layout process:
Pad Size
Adding a via hole to a pad increases its required size. The larger pad area can potentially cause spacing issues or overlap adjacent pads.
Capture Pad
A capture pad may be needed on inner layers to prevent the via barrel from being exposed. This consumes additional board space.
Thermal Relief
A thermal relief cutout may be required around the via to manage heat dissipation through the pad. This further increases pad area.
Plating Reliability
The via-pad connection must be sufficiently plated to avoid reliability risks. This may require design and process adjustments.
Hole Size
The via diameter must be smaller than permitted by the component but large enough for plating thickness.
Alignment
Layer-to-layer alignment accuracy must match the pad size and tolerance requirements dictated by the via location.
Stackup Planning
The layer change provided by the via must align with routing requirements. This impacts stackup design.
Stub Management
Any via stub should be minimized. This requires coordination of via length with layer change location.
Manufacturing Process
The assembly and board fabrication processes must support all design details like hole size, plating, and accuracy.
Electrical Design Guidelines
Several factors impact the electrical performance when using via-in-pad:
Reference Planes
Avoid referencing too many vias to a single plane. This can create resonances or allow noise coupling. Spread vias across multiple planes.
Antenna Diodes
Size pad area to avoid plasma etching during hole formation. Verify plating covers pad edge to prevent antenna effects.
Impedance Control
Model vias in pad to ensure impedance matches system requirements. This may require sizing pads for specific dielectric constants.
Resonances
Model for potential resonances at frequencies of interest. Verify any via stub resonances are well above operating bands.
Cross Talk
Model coupling between via transitions in adjacent pads within a package. Follow any spacing guidelines to avoid excessive coupling.
Current Flow
Consider thermal effects from current flow through pad vias. Verify traces do not overload a via with excessive current.
Mixed Signals
Keep digital and analog signals separated. Only place mixed signals together with proper isolation and grounding.
Following general high-speed design practices will help maximize electrical performance. Simulations using 3D EM tools are recommended to verify performance.
Thermal Design Guidelines
Via-in-pad also impacts thermal management. Key factors to consider include:
Heat Dissipation
Model expected heat dissipation through vias under maximum operating conditions. Ensure sufficient thermal conduction through all layers.
Thermal Relief
Include thermal cutouts as needed to avoid overheating pads during reflow when vias conduct heat into the pad.
Thermal Planes
Reference vias to thermal planes near hot components if possible. But avoid concentrating heat into small areas of a plane.
Ground Layers
Use several ground layer vias within a package to distribute and dissipate concentrated heat. But limit total ground layer area contacted to control resonances.
Dummy Vias
Add non-connected dummy vias with thermal reliefs in unused pad areas to improve thermal conduction.
Solder Voids
Avoid designs susceptible to solder voids blocking heat transfer from pad centers. This may require pad thermal modeling.
Plane Current
Consider pressure and current density resulting from concentrated heat dissipation into planes. Verify planes can handle max expected currents.
As always, thermal simulations using finite element modeling are highly recommended to validate the PCB thermal design.
Manufacturing Guidelines
Fabricating a design with via-in-pad requires close coordination with your board manufacturer. Key factors to discuss include:
Fab Notes
Provide complete notes defining all via-in-pad characteristics per their capabilities: locations, sizes, hole diameter, and plating requirements.
Tolerances
Confirm that specified hole size and location tolerances can be met relative to pad geometries.
Panel Design
Review panelization requirements to ensure via-in-pad pads are properly supported during board singulation.
Registration
Verify registration system accuracy meets overlay tolerances for stacking vias precisely within pads.
Aspect Ratio
Discuss maximum supported aspect ratio of hole depth to diameter. Confirm selected via sizes meet this spec.
Plating Reliability
Review plating process reliability at covering high density pad openings without voids at minimum design hole sizes.
Plating Thickness
Specify plating thickness requirements. Thicker plating improves reliability but reduces hole size.
Laser Drilling
Determine if laser drilling capability exists for required via hole sizes. Laser provides better accuracy than mechanical drilling.
Pad Design
Share pad size, shape, relief, and orientation information to check manufacturability.
Solder Mask
Specify if solder mask should cover, partially reveal, or fully reveal pad copper for soldering.
DFM
Ask manufacturer to run detailed design for manufacturing checks on your via-in-pad layout. Address any concerns or errors.
Close DFM communication with your board fab will help avoid manufacturability issues.
Component Selection Guidelines
Component package styles used with via-in-pad should be reviewed for compatibility:
Pad Size and Pitch
Verify component pads can accommodate necessary via-in-pad diameters while meeting spacing requirements.
Thermal Relief
Check if device pads require thermal reliefs. Avoid overlapping relief cutouts from adjacent pads.
Plating Barrier
Confirm component does not include internal pad plating barrier that could block via hole conduction.
Pad Shapes
Match via-in-pad shape to pad geometry. Avoid overlapping other pad features like orientation markers.
Density Capability
Select packages rated for via-in-pad density needed by design. Check manufacturer design guides.
Application Notes
Follow all device guidelines and application notes for utilization of vias within pads.
Qualification
Use component packages specifically qualified and tested by manufacturer for via-in-pad assembly.
Not all package types support equivalent via-in-pad implementation. Component selection and design should be verified to work together.
Layout Integration Guidelines
With electrical, thermal, and manufacturing considerations addressed, the PCB layout process can properly integrate via-in-pad:
Layer Planning
stacks. Confirm placement meets routing layer change requirements.
Capture Pads
Add capture pads on inner layers for each via-in-pad instance to isolate copper from hole barrel.
Plane Isolation
Surround all capture pads with isolation keepout on adjacent plane layers to prevent shorts.
Mechanical Layers
Create internal mechanical layers defining the specific via-in-pad locations and sizes to assist routing.
3D Modeling
Build 3D models with all pad and capture pad sizes and locations defined. Check for fit and interference issues.
Thermal Pads
Increase pad size as needed to accommodate thermal cutouts or improve heat conduction through traces.
Plane Relief
Add thermal reliefs to plane layers under each via to avoid excessive heat buildup during operation.
Net Names
Name all vias to clearly identify pins and nets being routed through each location.
With disciplines coordinated, PCB layout can implement all required details for proper functioning via-in-pad. Detailed design rule checking and cross probing in your CAD tool helps verify implementation.
Sample Via-in-Pad Layout Stackup
Here is an example 16 layer PCB stackup using via-in-pad technology for a large, high pin count BGA device:
| Layer | Layer Type |
|---|---|
| 1 | Top Solder |
| 2 | PWR |
| 3 | GND |
| 4 | Routing |
| 5 | GND |
| 6 | Routing |
| 7 | GND |
| 8 | Routing |
| 9 | CAPTURE |
| 10 | GND |
| 11 | Routing |
| 12 | GND |
| 13 | Routing |
| 14 | GND |
| 15 | PWR |
| 16 | Bottom Solder |
Key characteristics:
- Vias are placed in BGA pads on layers 1 through 8
- Capture pads added to layer 9 under all vias
- GND layers provide shielding between routing layers
- Multiple vias per pad distribute current and heat
- Plated through holes used for lower density peripheral pads
Via-in-Pad Design Example
To illustrate the implementation of via-in-pad, here is an example design steps for a QFN package signal pin pad:
1. Define Padstack
- Via diameter: 0.2mm
- Hole tolerance: 0.05mm
- Pad diameter: 0.6mm
- Finish: ENIG
- Layers: Top to GND2
2. Create Capture Pad
- 0.6mm capture pad on GND3 layer
- Clearance to plane edge: 0.2mm
3. Determine Routing Layers
- Top to GND1: Signal net
- GND1 to GND2: Ground via
4. Model Thermal Performance
- Simulate heat dissipation through pad
- Add thermal cutouts to avoid overheating
5. Generate 3D Pad Model
- Model padstack in MCAD tool
- Verify no interferences or spacing violations
6. Define Design Rules
- Netlisting
- Mask expansion
- Annular ring clearance
- Shorts checks
7. Layout Integration
- Place padstack array
- Route traces
- Validate design rules
This example reflects typical considerations and steps during integration of via-in-pad into a PCB design. Always refer back to guidelines and simulate performance to ensure successful implementation.
Via-in-Pad FQA
Below are answers to commonly asked questions about via-in-pad design and utilization:
What minimum clearance should be used around a via capture pad?
A clearance of at least 2 times the maximum plating thickness is recommended between a capture pad and adjacent copper. This ensures no shorting will occur.
Can multiple vias be placed in a single pad?
Yes, multiple vias are often used in an area array pad to improve routing access and thermal dissipation. Clearance between vias must be maintained.
What tolerances are required for via-in-pad registration?
Recommended tolerances are less than 25% of the pad to via annular ring width. This helps ensure the via properly aligns within the pad area.
Should solder mask be defined over a via-in-pad?
Partial solder mask definition helps control solder filleting while still allowing visual inspection of the via quality. Full mask or no mask approaches can also be used.
How does current carrying capacity compare between PTH and via-in-pad?
For the same via diameter, a typical via-in-pad has approximately 70% the current capacity of a plated through hole via.
Conclusion
Implementing via-in-pad requires coordination of electrical, thermal, and manufacturing constraints during PCB layout. When designed properly, the benefits of reduced congestion, simplified routing, and smaller product size can outweigh the added design considerations. As production capabilities continue improving, via-in-pad will become standard practice for dense electronic interconnects.
